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Silicon Labs /Series1 /EFM32GG12B /EFM32GG12B810F1024GM64 /LESENSE /IDLECONF

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Interpret as IDLECONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)CH00 (DISABLE)CH10 (DISABLE)CH20 (DISABLE)CH30 (DISABLE)CH40 (DISABLE)CH50 (DISABLE)CH60 (DISABLE)CH70 (DISABLE)CH80 (DISABLE)CH90 (DISABLE)CH10 0 (DISABLE)CH11 0 (DISABLE)CH12 0 (DISABLE)CH13 0 (DISABLE)CH14 0 (DISABLE)CH15

CH15=DISABLE, CH9=DISABLE, CH13=DISABLE, CH8=DISABLE, CH5=DISABLE, CH14=DISABLE, CH1=DISABLE, CH12=DISABLE, CH3=DISABLE, CH7=DISABLE, CH6=DISABLE, CH2=DISABLE, CH10=DISABLE, CH0=DISABLE, CH4=DISABLE, CH11=DISABLE

Description

GPIO Idle Phase Configuration

Fields

CH0

Channel 0 Idle Phase Configuration

0 (DISABLE): CH0 output is disabled in idle phase

1 (HIGH): CH0 output is high in idle phase

2 (LOW): CH0 output is low in idle phase

3 (DAC): CH0 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH1

Channel 1 Idle Phase Configuration

0 (DISABLE): CH1 output is disabled in idle phase

1 (HIGH): CH1 output is high in idle phase

2 (LOW): CH1 output is low in idle phase

3 (DAC): CH1 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH2

Channel 2 Idle Phase Configuration

0 (DISABLE): CH2 output is disabled in idle phase

1 (HIGH): CH2 output is high in idle phase

2 (LOW): CH2 output is low in idle phase

3 (DAC): CH2 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH3

Channel 3 Idle Phase Configuration

0 (DISABLE): CH3 output is disabled in idle phase

1 (HIGH): CH3 output is high in idle phase

2 (LOW): CH3 output is low in idle phase

3 (DAC): CH3 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH4

Channel 4 Idle Phase Configuration

0 (DISABLE): CH4 output is disabled in idle phase

1 (HIGH): CH4 output is high in idle phase

2 (LOW): CH4 output is low in idle phase

3 (DAC): CH4 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH5

Channel 5 Idle Phase Configuration

0 (DISABLE): CH5 output is disabled in idle phase

1 (HIGH): CH5 output is high in idle phase

2 (LOW): CH5 output is low in idle phase

3 (DAC): CH5 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH6

Channel 6 Idle Phase Configuration

0 (DISABLE): CH6 output is disabled in idle phase

1 (HIGH): CH6 output is high in idle phase

2 (LOW): CH6 output is low in idle phase

3 (DAC): CH6 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH7

Channel 7 Idle Phase Configuration

0 (DISABLE): CH7 output is disabled in idle phase

1 (HIGH): CH7 output is high in idle phase

2 (LOW): CH7 output is low in idle phase

3 (DAC): CH7 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH8

Channel 8 Idle Phase Configuration

0 (DISABLE): CH8 output is disabled in idle phase

1 (HIGH): CH8 output is high in idle phase

2 (LOW): CH8 output is low in idle phase

3 (DAC): CH8 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH9

Channel 9 Idle Phase Configuration

0 (DISABLE): CH9 output is disabled in idle phase

1 (HIGH): CH9 output is high in idle phase

2 (LOW): CH9 output is low in idle phase

3 (DAC): CH9 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH10

Channel 10 Idle Phase Configuration

0 (DISABLE): CH10 output is disabled in idle phase

1 (HIGH): CH10 output is high in idle phase

2 (LOW): CH10 output is low in idle phase

3 (DAC): CH10 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH11

Channel 11 Idle Phase Configuration

0 (DISABLE): CH11 output is disabled in idle phase

1 (HIGH): CH11 output is high in idle phase

2 (LOW): CH11 output is low in idle phase

3 (DAC): CH11 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH12

Channel 12 Idle Phase Configuration

0 (DISABLE): CH12 output is disabled in idle phase

1 (HIGH): CH12 output is high in idle phase

2 (LOW): CH12 output is low in idle phase

3 (DAC): CH12 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH13

Channel 13 Idle Phase Configuration

0 (DISABLE): CH13 output is disabled in idle phase

1 (HIGH): CH13 output is high in idle phase

2 (LOW): CH13 output is low in idle phase

3 (DAC): CH13 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH14

Channel 14 Idle Phase Configuration

0 (DISABLE): CH14 output is disabled in idle phase

1 (HIGH): CH14 output is high in idle phase

2 (LOW): CH14 output is low in idle phase

3 (DAC): CH14 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15
CH15

Channel 15 Idle Phase Configuration

0 (DISABLE): CH15 output is disabled in idle phase

1 (HIGH): CH15 output is high in idle phase

2 (LOW): CH15 output is low in idle phase

3 (DAC): CH15 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 0, 1, 2, 3, 12, 13, 14, 15

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data